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general description the MAX8759 integrated cold-cathode fluorescent lamp (ccfl) inverter controller is designed to drive ccfls using a full-bridge resonant inverter. the resonant opera- tion ensures reliable striking and provides near-sinusoidal waveforms over the entire input range. the controller operates over a wide input-voltage range of 4.5v to 28v with high power to light efficiency. the device also includes safety features that effectively protect against single-point fault conditions such as lamp-out, secondary overvoltage, and secondary short-circuit faults. the MAX8759 provides accurate lamp-current regula- tion ( 2.5%) for superior ccfl inverter performance. the lamp current is adjustable with an external resistor; 10:1 dimming range can be achieved by turning the ccfl on and off using a digital pulse-width modulation (dpwm) method, while maintaining the lamp-current constant. the MAX8759 provides three mechanisms for controlling brightness: 2-wire smbus-compatible interface, external ambient-light sensor (als), or sys- tem pwm control. the MAX8759 supports intel display power-saving technology (dpst) to maximize battery life. the device includes two lamp-current feedback input pins that support dual-lamp applications with a minimum number of external components. the MAX8759 controls a full-bridge inverter for maxi- mum efficiency and directly drives four external n-chan- nel power mosfets. an internal 5.35v linear regulator powers the mosfet drivers and most of the internal circuitry. the MAX8759 is available in a space-saving, 28-pin, thin qfn package and operates over a -40? to +85? temperature range. applications notebooks lcd monitors automotive infotainment features ? accurate dimming control using smbus, pwm interface, or ambient light sensor ? 10:1 dimming range with 256-step resolution ? resonant-mode operation longer lamp life with near sinusoidal lamp- current waveform guaranteed striking capability high-power-to-light efficiency ? wide input-voltage range (4.5v to 28v) ? input feed-forward for excellent line rejection ? ?.5% lamp-current regulation ? adjustable 1.5% accurate dpwm frequency ? dual lamp-current feedback inputs ? comprehensive fault protection secondary voltage limiting primary current limit with lossless sensing lamp-out protection with adjustable timeout secondary short-circuit protection ? small 28-pin, 5mm x 5mm, thin qfn package MAX8759 low-cost, smbus, ccfl backlight controller ________________________________________________________________ maxim integrated products 1 ordering information MAX8759 minimal operating circuit 19-3874; rev 1; 2/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package pkg code MAX8759eti+ -40 c to +85 c 28 thin qfn-ep* 5mm 5mm t2855-6 + denotes lead-free package. * ep = exposed pad. pin configuration appears at end of data sheet. smbus is a trademark of intel corp.
MAX8759 low-cost, smbus, ccfl backlight controller 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1, v batt = 12v, v cc = v dd, t a = 0? to +85? . typical values are at t a = +25 c, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. batt to gnd..........................................................-0.3v to +30v bst1, bst2 to gnd ...............................................-0.3v to +36v bst1 to lx1, bst2 to lx2 ........................................-0.3v to +6v freq, v cc , v dd to gnd .........................................-0.3v to +6v sda, scl to gnd.....................................................-0.3v to +6v als, comp, pwmi, pwmo, tflt, del, vals to gnd .......................-0.3v to (v cc + 0.3v) gh1 to lx1 ..............................................-0.3v to (v bst1 + 0.3v) gh2 to lx2 ..............................................-0.3v to (v bst2 + 0.3v) gl1, gl2 to gnd .......................................-0.3v to (v dd + 0.3v) ifb1, ifb2, isec, vfb to gnd ....................................-3v to +6v pgnd1, pgnd2 to gnd .......................................-0.3v to +0.3v continuous power dissipation (t a = +70 c) 28-pin thin qfn 5mm x 5mm (derate 21.3mw/ c above +70 c) .............................1702mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter conditions min typ max units v cc = v dd = v batt 4.5 5.5 batt input voltage range v cc = v dd = open 5.5 28.0 v v batt = 28v 2.5 5 batt quiescent current MAX8759 is enabled v batt = v cc = 5v 5 ma batt quiescent current, shutdown MAX8759 is disabled 0.1 2 a v cc output voltage, normal operation MAX8759 is enabled, 6v < v batt < 28v, 0 < i load < 10ma 5.2 5.35 5.5 v v cc output voltage, shutdown MAX8759 is disabled, no load 3.5 4.3 5.5 v v cc rising (leaving lockout) 4.3 v cc undervoltage lockout threshold v cc falling (entering lockout) 3.7 v v cc undervoltage lockout hysteresis 230 mv v cc por threshold rising edge 1.75 v v cc por hysteresis 50 mv gh1, gh2, gl1, gl2 on-resistance, low state i test = 100ma, v cc = v dd = 5v 3 6 ? gh1, gh2, gl1, gl2 on-resistance, high state i test = 100ma, v cc = v dd = 5v 10 18 ? bst1, bst2 leakage current v bst _ = 12v, v lx _ = 7v 4 10 a resonant frequency range guaranteed by design 30 80 khz minimum on-time 350 500 700 ns maximum off-time 40 60 80 ? current-limit threshold lx1 - pgnd1, lx2 - pgnd2 415 430 445 mv zero-current-crossing threshold lx1 - pgnd1, lx2 - pgnd2 3 8 13 mv current-limit leading-edge blanking 350 ns ifb1, ifb2 input-voltage range -3 +3 v ifb1 regulation point 765 785 805 mv ifb2 regulation point 780 800 820 mv
MAX8759 low-cost, smbus, ccfl backlight controller _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v batt = 12v, v cc = v dd, t a = 0? to +85? . typical values are at t a = +25 c, unless otherwise noted.) parameter conditions min typ max units 0 < v ifb1,2 < 3v -3 +3 ifb1, ifb2 input bias current -3v < v ifb1,2 < 0 -230 ? ifb1, ifb2 lamp-out threshold 575 600 625 mv ifb1, ifb2 to comp transconductance 0.5v < v comp < 4v 60 100 160 ? comp output impedance 61224m ? comp discharge current during overvoltage or overcurrent fault v vfb = 2.6v or v isec = 1.5v 500 1000 2000 ? comp discharge current during dpwm off-time v comp = 1.5v 90 110 130 ? dpwm rising-to-falling ratio v ifb1,2 = 0 2.5 isec input voltage range -3 +3 v isec overcurrent threshold 1.18 1.21 1.26 v isec input bias current v isec = 1.25v -0.3 +0.3 a vfb input voltage range -4 +4 v vfb input impedance 150 300 450 m ? vfb overvoltage threshold 2.2 2.3 2.4 v vfb undervoltage threshold 210 240 280 mv vfb undervoltage delay r freq = 169k ? 250 ? r freq = 169k ? , t a = +25? to +85? 207 210 213 r freq = 169k ? 205 210 215 r freq = 340k ? 106 dpwm oscillator frequency r freq = 100k ? 343 hz pwmo output impedance 20 40 60 k ? pwmi input low voltage 0.7 v pwmi input high voltage 2.1 v pwmi input hysteresis 300 mv pwmi input bias current -0.3 +0.3 a pwmi input frequency range 5 50 khz pwmi full-range accuracy 5 lsb pwmi duty cycle = 100% 98 100 pwmi duty cycle = 50% 48 50 52 pwmi brightness setting pwmi duty cycle = 0% 9.7 10.0 10.3 % als full-adjustment range 0 1.8 v als full-range accuracy 5 lsb als input bias current -0.1 +0.1 a vals output voltage MAX8759 is enabled, 6v < v batt < 28v, i load = 1ma 5.10 5.30 5.50 v vals leakage current MAX8759 is disabled, vals = gnd -3 +3 ? vals on-resistance MAX8759 is enabled 30 60 ?
MAX8759 low-cost, smbus, ccfl backlight controller 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v batt = 12v, v cc = v dd, t a = 0? to +85? . typical values are at t a = +25 c, unless otherwise noted.) parameter conditions min typ max units v batt = 9v, r thr = 120k ? 0 0.15 0.30 zero-crossing delay v batt = 12v, r thr = 120k ? 1.50 1.80 2.10 ? maximum zero-crossing delay v batt = 18v, r thr = 120k ? 3.2 3.8 4.4 ? del rising 4.5 del disable threshold del falling 3.8 v v isec < 1.25v and v ifb < 540mv; v flt = 2v 0.9 1.0 1.1 v isec < 1.25v and v ifb > 660mv; v flt = 2v -1.5 -1.2 -0.8 tflt charge current v isec > 1.25v and v ifb > 660mv; v flt = 2v 115 135 155 ? tflt trip threshold rising edge 3.7 4 4.3 v sda, scl, input low voltage 0.7 v sda, scl, input high voltage 2.1 v sda, scl, input hysteresis 100 mv sda, scl, input bias current -1 +1 ? sda output low sink current v sda = 0.4v 4 ma smbus frequency 10 100 khz smbus free time t buf 4.7 1 s scl serial clock high period t high 4s scl serial clock low period t low 4.7 ? start condition setup time t su:sta 4.7 ? start condition hold time t hd:sta 4s stop condition setup time from scl t su:sto 4s sda valid to scl rising-edge setup time, slave clocking in data t su:dat 250 ns scl falling edge to sda transition t hd:dat 0ns scl falling edge to sda valid, reading out data t dv 200 ns
MAX8759 low-cost, smbus, ccfl backlight controller _______________________________________________________________________________________ 5 electrical characteristics (circuit of figure 1, v batt = 12v, v cc = v dd, t a = -40? to +85? .) (note 1) parameter conditions min typ max units v cc = v dd = v batt 4.5 5.5 batt input voltage range v cc = v dd = open 5.5 28.0 v v batt = 28v 5 batt quiescent current MAX8759 is enabled v batt = v cc = 5v 5 ma v cc output voltage, normal operation MAX8759 is enabled, 6v < v batt < 28v, 0 < i load < 10ma 5.2 5.5 v v cc output voltage, shutdown MAX8759 is disabled, no load 3.5 5.5 v v cc rising (leaving lockout) 4.3 v cc undervoltage lockout threshold v cc falling (entering lockout) 3.7 v gh1, gh2, gl1, gl2 on-resistance, low state i test = 100ma, v cc = v dd = 5v 6 ? gh1, gh2, gl1, gl2 on-resistance, high state i test = 100ma, v cc = v dd = 5v 18 ? resonant frequency range guaranteed by design 30 80 khz minimum on-time 350 700 ns maximum off-time 40 80 ? current-limit threshold lx1 - pgnd1, lx2 - pgnd2 410 450 mv zero-current crossing threshold lx1 - pgnd1, lx2 - pgnd2 3 13 mv ifb1, ifb2 input voltage range -3 +3 v ifb1 regulation point 760 810 mv ifb2 regulation point 775 825 mv ifb1, ifb2 input bias current -3v < v ifb1,2 < 0 -230 ? ifb1, ifb2 lamp-out threshold 565 635 mv ifb1, ifb2 to comp transconductance 0.5v < v comp < 4v 60 160 ? comp output impedance 625m ? comp discharge current during overvoltage or overcurrent fault v vfb = 2.6v or v isec = 1.5v 500 2000 ? comp discharge current during dpwm off-time v comp = 1.5v 90 130 ? isec input voltage range -3 +3 v isec overcurrent threshold 1.18 1.26 v vfb input voltage range -4 +4 v vfb input impedance 150 450 m ? vfb overvoltage threshold 2.2 2.4 v vfb undervoltage threshold 210 280 mv dpwm oscillator frequency r freq = 169k ? 203 217 hz pwmo output impedance 20 60 k ?
MAX8759 low-cost, smbus, ccfl backlight controller 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v batt = 12v, v cc = v dd, t a = -40? to +85? .) (note 1) parameter conditions min typ max units pwmi input low voltage 0.7 v pwmi input high voltage 2.1 v pwmi input frequency range 5 50 khz pwmi duty cycle = 100% 98 pwmi duty cycle = 50% 48 52 pwmi brightness setting pwmi duty cycle = 0% 9.7 10.3 % als full-adjustment range 0 1.8 v vals output voltage MAX8759 is enabled, 6v < v batt < 28v, i load = 1ma 5.10 5.50 v vals on-resistance MAX8759 is enabled 60 ? v batt = 9v, r thr = 100k ? 0 0.3 zero-crossing delay v batt = 12v, r thr = 100k ? 1.50 2.10 ? maximum zero-crossing delay v batt = 16v, r thr = 100k ? 3.2 4.4 ? del rising 4.5 del disable threshold del falling 3.9 v v isec < 1.25v and v ifb < 540mv; v flt = 2v 0.8 1.2 v isec < 1.25v and v ifb > 660mv; v flt = 2v -1.5 -0.8 tflt charge current v isec > 1.25v and v ifb > 660mv; v flt = 2v 115 155 ? tflt trip threshold rising edge 3.7 4.3 v sda, scl, input low voltage 0.7 v sda, scl, input high voltage 2.1 v sda output low-sink current v sda = 0.4v 4 ma smbus frequency 10 100 khz smbus free time t buf 4.7 ? scl serial clock high period t high 4s scl serial clock low period t low 4.7 ? start condition setup time t su:sta 4.7 ? start condition hold time t hd:sta 4s stop condition setup time from scl t su:sto 4s sda valid to scl rising-edge setup time, slave clocking in data t su:dat 250 ns scl falling edge to sda transition t hd:dat 0ns scl falling edge to sda valid, reading out data t dv 200 ns note 1: specifications to -40? are guaranteed by design, not production tested.
MAX8759 low-cost, smbus, ccfl backlight controller _______________________________________________________________________________________ 7 c d b a a: vfb, 2v/div b: lx1, 10v/div low-input voltage operation (v in = 8.0v) MAX8759 toc01 10 s/div c: lx2, 10v/div d:ifb, 2v/div c d b a a: vfb, 2v/div b: lx1, 20v/div high-input voltage operation (v in = 20.0v) MAX8759 toc02 10 s/div c: lx2, 20v/div d: ifb, 2v/div c d b a a: v in , 10v/div b: comp, 2v/div line transient response (8v to 20v) MAX8759 toc03 100 s/div c: ifb, 2v/div d: lx1, 20v/div c d b a a: v in , 10v/div b: comp, 2v/div line transient response (20v to 8v) MAX8759 toc04 100 s/div c: ifb, 2v/div d: lx1, 20v/div c b a a: vfb, 2v/div b: comp, 1v/div minimum brightness startup waveform (smbus mode, brightness register = 0x00) MAX8759 toc05 2ms/div c: ifb, 2v/div c b a a: vfb, 2v/div b: comp, 1v/div minimum brightness dpwm operation (smbus mode, brightness register = 0x00) MAX8759 toc06 2ms/div c: ifb, 2v/div c b a a: vfb, 2v/div b: comp, 1v/div 50% brightness dpwm operation (smbus mode, brightness register = 0x80) MAX8759 toc07 2ms/div c: ifb, 2v/div c b a a: vfb, 2v/div b: comp, 1v/div dpwm soft-start MAX8759 toc08 40 s/div c: ifb, 2v/div c b a a: vfb, 2v/div b: comp, 1v/div dpwm soft-stop MAX8759 toc09 40 s/div c: ifb, 2v/div typical operating characteristics (circuit of figure 1, v in = 12v, v cc = v dd , t a = +25 c, unless otherwise noted.)
MAX8759 low-cost, smbus, ccfl backlight controller 8 _______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v cc = v dd , t a = +25 c, unless otherwise noted.) c b a a: vfb, 2v/div b: comp, 500mv/div open-lamp voltage limiting and timeout MAX8759 toc010 200ms/div c: tflt, 5v/div c b a a: isec, 2v/div b: comp, 1v/div secondary short-circuit protection and timeout MAX8759 toc011 2ms/div c: tflt, 1v/div 30 40 60 50 70 80 switching frequency vs. input voltage MAX8759 toc12 v in (v) switching frequency (khz) 515 10 20 25 50 150 100 250 200 300 350 dpwm frequency vs. r freq MAX8759 toc13 r freq (k ? ) dpwm frequency (hz) 50 150 200 100 250 300 350 3 4 6 5 7 8 rms lamp current vs. input voltage MAX8759 toc14 input voltage (v) rms lamp current (ma) 515 10 20 25 i lamp = 7ma i lamp = 6ma i lamp = 5ma i lamp = 4ma 5.6 5.8 5.7 6.0 5.9 6.1 6.2 515 10 20 25 rms lamp current (i lamp = 6ma) vs. input voltage MAX8759 toc15 input voltage (v) rms lamp current (ma) 0 20 60 40 80 100 00.4 0.2 0.6 0.8 1.0 normalized brightness vs. pwmi duty cycle MAX8759 toc17 pwmi duty ratio normalized brightness (%) 0 20 60 40 80 100 00.8 0.4 1.2 1.6 2.0 normalized brightness vs. als voltage MAX8759 toc18 v als (v) normalized brightness (%) 0 20 60 40 80 100 040 20 60 80 100 normalized brightness vs. smbus brightness setting MAX8759 toc16 brightness setting (%) normalized brightness (%)
MAX8759 low-cost, smbus, ccfl backlight controller _______________________________________________________________________________________ 9 0 20 60 40 80 100 00.4 0.2 0.6 0.8 1.0 normalized brightness vs. smbus brightness and pwmi duty cycle MAX8759 toc19 pwmi duty ratio normalized brightness (%) smb = 0xff smb = 0x80 0 0.2 0.6 0.4 0.8 1.0 00.4 0.2 0.6 0.8 1.0 normalized brightness vs. als voltage and pwmi duty cycle MAX8759 toc20 pwmi duty ratio v als = 1.8v v als = 1.8v v als = 0.8v b a als transient response (alsdel1 = alsdel0 = 0) MAX8759 toc21 a: als, 1v/div b: comp, 1v/div 1s/div 5.30 5.31 5.33 5.32 5.34 5.35 v cc line regulation MAX8759 toc22 input voltage (v) v cc voltage (v) 816 12 20 24 5.30 5.31 5.33 5.32 5.34 5.35 04 2681012 v cc load regulation MAX8759 toc23 load current (ma) v cc voltage (v) v in = 24v v in = 12v 5.27 5.28 5.30 5.29 5.31 5.32 -40 0 -20 20 40 60 80 v cc voltage vs. temperature MAX8759 toc24 temperature ( c) v cc voltage (v) typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v cc = v dd , t a = +25 c, unless otherwise noted.)
MAX8759 low-cost, smbus, ccfl backlight controller 10 ______________________________________________________________________________________ pin description pin name function 1 batt supply input. batt is the input to the internal 5.35v linear regulator that powers the device. bypass batt to gnd with a 0.1? ceramic capacitor. 2 sda smbus serial data input 3 scl smbus serial clock input 4 tflt fault-timer adjustment pin. connect a capacitor from tflt to gnd to set the time-out periods for open- lamp and secondary overcurrent faults. 5 vals ambient-light-sensor supply pin. bypass vals to gnd with a 0.1? capacitor. 6 als ambient-light-sensor input 7 pwmi dpst control input 8 pwmo dpst buffer output. connect a capacitor between pwmo and gnd. the capacitor forms a lowpass filter with an internal 40k ? (typ) resistor for filtering the dpst signal. 9 freq chopping-frequency adjustment pin. connect a resistor from freq to gnd to set the dpwm frequency: f dpwm = 210hz 169k ? / r freq . 10 comp transconductance error amplifier output. a compensation capacitor connected between comp and gnd sets the rise and fall time of the lamp-current envelope in dpwm operation. 11 del adaptive zero-crossing-delay adjustment pin. connect a resistor between del and gnd to adjust the range of the zero-crossing delay. connecting del to v cc disables the zero-crossing delay function. 12 ifb1 lamp-current-feedback input. the ifb1 sense signal is internally full-wave rectified. ifb1 is compared with ifb2 and the larger is used for lamp-current regulation. the average value of the rectified signal is regulated to 785mv (typ) by controlling the on-time of high-side switch. an open-lamp fault is generated if the peak voltage of ifb1 is below 600mv for a fault delay period set by tflt. 13 ifb2 lamp-current-feedback input. the ifb2 sense signal is internally full-wave rectified. ifb1 is compared with ifb2 and the larger is used for lamp-current regulation. the average value of the rectified signal is regulated to 800mv (typ) by controlling the on-time of high-side switch. an open-lamp fault is generated if the peak voltage of ifb2 is below 600mv for a fault-delay period set by tflt. ifb2 input can be disabled by connecting ifb2 to v cc . 14 vfb transformer secondary voltage-feedback input. a capacitive voltage-divider between the high-voltage terminal of the ccfl tube and gnd sets the maximum average lamp voltage during striking and lamp-out fault. when the peak voltage on vfb exceeds the internal overvoltage threshold, the controller turns on an internal current sink, discharging the comp capacitor to limit the switch on-time. the vfb pin is also used to detect a secondary undervoltage condition. if the peak voltage on vfb is below 230mv continuously for 250? during the dpwm on period, the MAX8759 shuts down. 15 isec transformer secondary current-feedback input. a current-sense resistor connected between the low- voltage end of the transformer secondary and the ground sets the maximum secondary current during short-circuit fault. when the peak voltage on isec exceeds the internal overcurrent threshold, the controller turns on an internal current sink discharging the comp capacitor. 16 lx1 gh1 gate-driver return. lx1 is the input to the current-limit and zero-crossing comparators. the device senses the voltage across the low-side mosfet nl1 to detect primary current zero crossing and primary overcurrent. 17 gh1 high-side mosfet nh1 gate driver output
MAX8759 low-cost, smbus, ccfl backlight controller ______________________________________________________________________________________ 11 pin name function 18 bst1 gh1 gate-driver supply input. connect a 0.1? capacitor from lx1 to bst1. 19 pgnd1 power ground. pgnd1 is the return for the gl1 gate driver. 20 gl1 low-side mosfet nl1 gate driver output 21 v dd low-side gate-driver supply input. connect v dd to the output of the internal linear regulator (v cc ). 22 gl2 low-side mosfet nl2 gate-driver output 23 pgnd2 power ground. pgnd2 is the return for the gl2 gate driver. 24 bst2 gh2 gate-driver supply input. connect a 0.1? capacitor from lx2 to bst2. 25 gh2 high-side mosfet nh2 gate-driver output 26 lx2 gh2 gate-driver return. lx2 is the input to the current-limit and zero-crossing comparators. the device senses the voltage across the low-side mosfet nl2 to detect primary current zero crossing and primary overcurrent. 27 gnd analog ground. the ground return for v cc , ref, and other analog circuitry. connect gnd to pgnd under the ic at the ic? backside exposed metal pad. 28 v cc 5.35v/10ma internal linear-regulator output. v cc is the supply voltage for the device. bypass v cc with a 0.47? ceramic capacitor to gnd. ep exposed backside pad. connect pad to gnd. pin description (continued)
MAX8759 low-cost, smbus, ccfl backlight controller 12 ______________________________________________________________________________________ n2a 19 24 21 21 c7 0.1 f c8 0.47 f c1 10 f 25v c10 0.1 f c11 0.1 f c13 6.8nf c6 68nf c5 10nf c4 10pf 3kv c2 2.2 f c3 2.2 f t1 1:110 r1 150 ? 1% ccfl r2 3.9k ? c14 0.22 f fdc6561an fdc6561an c9 0.47 f c12 1 f c15 0.1 f r3 169k ? 1% v cc 27 11 28 2 3 7 8 9 5 6 batt gnd del v cc sda scl pwmi pwmo freq vals als 18 17 16 26 20 23 22 25 12 13 v cc 14 15 10 4 pgnd1 bst2 v dd bst1 gh1 lx1 lx2 gl1 pgnd2 gl2 gh2 ifb1 ifb2 vfb isec comp tflt n2b n1a n1b pwm input input voltage smb_data smb_clock f1 2a als supply als output 7.5v to 24v MAX8759 figure 1. typical MAX8759 single-lamp operating circuit
MAX8759 low-cost, smbus, ccfl backlight controller ______________________________________________________________________________________ 13 typical operating circuit the MAX8759 typical operating circuit (figure 1) is a single-lamp ccfl backlight inverter for notebook com- puter tft lcd panels. the input voltage range of the circuit is from 7.5v to 24v. the maximum rms lamp current is set to 6ma and the maximum rms striking voltage is set to 1800v. table 1 lists some important components and table 2 lists the component suppliers contact information. detailed description the MAX8759 controls a full-bridge resonant inverter to convert an unregulated dc input into a high-frequency ac output for powering ccfls. the resonant operation maximizes striking capability and provides near-sinu- soidal waveforms over the entire input range to improve ccfl lifetime. the lamp brightness is adjusted by turn- ing the lamp on and off with a dpwm signal. the dpwm frequency can be accurately adjusted with a resistor. the brightness of the lamp is proportional to the duty cycle of the dpwm signal, which is controlled either with a 2-wire smbus-compatible interface, with an external als, or with an external pwm signal. the device also includes safety features that effectively pro- tect against single-point fault conditions such as lamp- out and secondary short-circuit faults. an internal 5.35v linear regulator powers the mosfet drivers and most of the internal circuitry. figure 2 is the functional dia- gram of the MAX8759 and figure 3 is the detailed dia- gram of the smbus and als input block. resonant operation the MAX8759 drives four n-channel power mosfets that make up the zero-voltage-switching (zvs) full- bridge inverter as shown in figure 4. assume that nh1 and nl2 are on at the beginning of a switching cycle as shown in figure 4(a). the primary current flows through mosfet nh1, dc blocking capacitor c2, the primary side of transformer t1, and mosfet nl2. during this interval, the primary current ramps up until the controller turns off nh1. when nh1 is turned off, the primary current forward biases the body diode of nl1, which clamps the lx1 voltage just below ground as shown in figure 4(b). when the controller turns on nl1, its drain-to-source voltage is near zero because its for- ward-biased body diode clamps the drain. since nl2 is still on, the primary current flows through nl1, c2, the primary side of t1, and nl2. once the primary cur- rent drops to the minimum current threshold (6mv/r ds(on) ), the controller turns off nl2. the remaining energy in t1 charges up the lx2 node until the body diode of nh2 is forward biased. when nh2 turns on, it does so with near-zero drain-to-source volt- age. the primary current reverses polarity as shown in figure 4(c), beginning a new cycle with the current flowing in the opposite direction, with nh2 and nl1 on. the primary current ramps up until the controller turns off nh2. when nh2 is turned off, the primary current forward biases the body diode of nl2, which clamps the lx2 voltage just below ground as shown in figure 4(d). after the lx2 node goes low, the controller loss- lessly turns on nl2. once the primary current drops to the minimum current threshold, the controller turns off nl1. the remaining energy charges up the lx1 node until the body diode of nh1 is forward biased. finally, nh1 losslessly turns on, beginning a new cycle as shown in figure 4(a). note that switching transitions on all four power mosfets occur under zvs conditions, which reduces transient power losses and emi. designation description c1 10? ?0%, 25v x5r ceramic capacitor (1210) murata grm32dr61e106m tdk c3225x5r1e106m c2, c3 2.2? ?0%, 25v x5r ceramic capacitors (0805) murata grm21br61e225k tdk c2012x5r1e225k c4 10pf ?0%, 3kv hv ceramic capacitor (1808) kemet c1808c100khgac tdk c4520c0g3f100f nh1/2, nl1/2 dual n-channel mosfets, 30v, 0.095 ? , 6-pin sot23 fairchild fdc6561an t1 ccfl transformer, 1:110 turns ratio tmp ui9.8l type table 1. list of important components supplier website fairchild semiconductor www.fairchildsemi.com kemet www.kemet.com murata www.murata.com tdk www.components.tdk.com tmp www.tmp.com table 2. component suppliers
MAX8759 low-cost, smbus, ccfl backlight controller 14 ______________________________________________________________________________________ figure 2. MAX8759 functional diagram MAX8759 linear regulator bias 4.3v rdy en smbus dwpm osc als adc brightness control 8-bit counter pwm adc 40k ? s r q batt v cc vals isec scl freq sda als pwmi pwmo dpwm latch dpwm comp s r q v cc oc comp uvlo comparator batt gnd max fw fw ov comp oc oc 1.21v open-lamp comp 600mv 135 a 1 a z x 2.3v vfb comp ifb1 ifb2 1000 a 100 a rdy error amp v ref mux lx_ zx ilim comp 400mv pwm comp bst1 gh1 dh dh dl dl lx1 bst2 gh2 lx2 vdd gl1 pgnd2 gl2 gate-driver control state machine r ton ff min ton s q q zero-cross detections and delay block pgnd1 del s r q shutdown fault latch 230mv vfb uv comp tflt 4v min
MAX8759 low-cost, smbus, ccfl backlight controller ______________________________________________________________________________________ 15 figure 3. MAX8759 smbus and ambient-light-sensor input block als status register als low-limit register als high-limit register als clamp bright control register device control register mux digital multiplier buffer digital pot smbus interface dpwm setting pwmi sda scl 0x04 0x00 0x01 0x06 0x05 mux "1" pwmo als smbus and ambient-light-sensor input block inverter on/off mux pwm_sel als_ctl pwm_md buffer fault/ status register 0x02 offset a d a d a simplified ccfl inverter circuit is shown in figure 5 (a). the full-bridge power stage is simplified and repre- sented as a square-wave ac source. the resonant tank circuit can be further simplified to figure 5(b) by removing the transformer. c s is the primary series capacitor, c s ?is the series capacitance reflected to the secondary, c p is the secondary parallel capacitor, n is the transformer turns ratio, l is the transformer sec- ondary leakage inductance, and r l is an idealized resistance that models the ccfl in normal operation. figure 6 shows the frequency response of the resonant tank? voltage gain under different load conditions. the primary series capacitor is 1?, the secondary parallel capacitor is 15pf, the transformer turns ratio is 1:93, and the secondary leakage inductance is 260mh. notice that there are two peaks, f s, and f p , in the fre- quency response. the first peak f s is the series reso- nant peak determined by the secondary leakage inductance (l) and the series capacitor reflected to the secondary (c s ): f 1 2lc s s =
MAX8759 the second peak f p is the parallel resonant peak deter- mined by the secondary leakage inductance (l), the parallel capacitor (c p ), and the series capacitor reflect- ed to the secondary (c s ): the inverter is designed to operate between these two resonant peaks. when the lamp is off, the operating point of the resonant tank is close to the parallel reso- nant peak due to the lamp? infinite impedance. the cir- cuit displays the characteristics of a parallel-loaded resonant converter. while in parallel-loaded resonant operation, the inverter behaves like a voltage source to generate the necessary striking voltage. theoretically, the output voltage of the resonant converter increases until the lamp is ionized or until it reaches the ic? sec- ondary voltage limit. once the lamp is ionized, the equivalent load resistance decreases rapidly and the operating point moves toward the series resonant peak. while in series resonant operation, the inverter behaves like a current source. lamp-current regulation the MAX8759 uses a lamp-current control loop to regu- late the current delivered to the ccfl. the heart of the control loop is a transconductance error amplifier. the f l cc cc p sp sp = + 1 2 low-cost, smbus, ccfl backlight controller 16 ______________________________________________________________________________________ t1 c2 v batt (a) nh1 on nl1 off nh2 off nl2 on lx2 lx1 t1 c2 v batt (b) nh1 off nl1 on nh2 off nl2 on lx2 lx1 t1 c2 v batt (c) nh1 off nl1 on nh2 on nl2 off lx2 lx1 t1 c2 v batt (d) nh1 off nl1 on nh2 off nl2 on lx2 lx1 (body diode turns on first) (body diode turns on first) figure 4. resonant operation
ac lamp current is sensed with a resistor connected in series with the low-voltage terminal of the lamp. the MAX8759 has two lamp-current feedback inputs (ifb1 and ifb2) to support dual-lamp application. the volt- ages across the sense resistors are fed to the ifb1 and ifb2 inputs and are internally full-wave rectified. the transconductance error amplifier selects the higher one of the two feedback signals and compares the rectified voltage with an internal threshold to generate an error current. the error current charges and discharges a capacitor connected between comp and ground to create an error voltage (v comp ). v comp is then com- pared with an internal ramp signal to set the high-side mosfet switch on-time (t on ). feed-forward control the MAX8759 is designed to maintain tight control of the lamp current under all transient conditions. the feed-forward control instantaneously adjusts the on- time for changes in input voltage (v batt ). this feature provides immunity to input-voltage variations and sim- plifies loop compensation over wide input-voltage ranges. the feed-forward control also improves the line regulation for short dpwm on-times and makes startup transients less dependent on the input voltage. feed-forward control is implemented by increasing the internal voltage ramp rate for higher v batt . this has the effect of varying t on as a function of the input volt- age while maintaining approximately the same signal levels at v comp . since the required voltage change across the compensation capacitor is minimal, the con- troller? response to input voltage changes is essentially instantaneous. lamp startup a ccfl is a gas-discharge lamp that is normally driven in the avalanche mode. to start ionization in a nonionized lamp, the applied voltage (striking voltage) must be increased to the level required for the start of avalanche. at low temperatures, the striking voltage can be several times the typical operating voltage. because of the MAX8759? resonant topology, the striking voltage is guaranteed. before the lamp is ionized, the lamp impedance is infinite. the transformer secondary leakage inductance and the high-voltage parallel capaci- tor determine the unloaded resonant frequency. since the unloaded resonant circuit has a high q, it can generate very high voltage across the lamp. MAX8759 low-cost, smbus, ccfl backlight controller ______________________________________________________________________________________ 17 ac source ccfl c p l c s 1:n (a) ac source r l c p l c' s = (b) c s n 2 figure 5. equivalent resonant tank circuit frequency (khz) voltage gain (v/v) 80 60 40 20 1 2 3 4 0 0 100 r l increasing figure 6. frequency response of the resonant tank
MAX8759 dimming control the MAX8759 controls the brightness of the ccfl by ?hopping?the lamp current on and off using a low-fre- quency (between 100hz and 350hz) dpwm signal. the frequency of the internal dpwm oscillator is adjustable through a resistor connected between the freq pin and gnd. the ccfl brightness is propor- tional to the dpwm duty cycle, which can be adjusted from 10.15% to 100%. in dpwm operation, the comp voltage controls the dynamics of the lamp-current envelope. at the begin- ning of the dpwm on cycle, the average value of the lamp-current feedback signal is below the regulation point, so the transconductance error amplifier sources current into the comp capacitor. the switch on-time (t on ) gradually increases as v comp rises, which pro- vides soft-start. at the end of the dpwm on cycle, the MAX8759 turns on a 110? internal current source. the current source linearly discharges the comp capacitor, gradually decreasing t on , and providing soft-stop. the dpwm frequency can be set with an external resis- tor. connect a resistor between freq and gnd. the dpwm frequency is given by the following equation: the adjustable range of the dpwm frequency is between 100hz and 350hz (r freq is between 100k ? and 350k ? ). the MAX8759 has three ways for brightness control. the brightness can be controlled by a 2-wire serial interface (smbus), by an external pwm signal, or by an external ambient-light sensor signal. there are five operating modes, which can be selected by setting bits 1 to 3 in device control register 0x01 (see the smbus register definitions section for details). als mode the MAX8759 can work with several types of ambient- light sensors. the ideal ambient-light sensors should have a linear response to ambient light and should have a spectral response equivalent to that of the human eye. ambient-light sensors must provide filtering of low-frequency harmonics found in the electrical spectrum of the many light sources. the als? output should be a dc analog voltage that is linearly propor- tional to the ambient luminance. in als mode, the MAX8759 sets the brightness based on the analog voltage on the als pin. the als pin is connected to the output of an external ambient-light sensor. the usable input-voltage range of the als pin is 0 to 1.8v. the MAX8759 compares the als input voltage against user-programmable low and high limits. when the als input voltage is below the low limit, the brightness is clamped to the als low limit. when the als i nput voltage is above the high limit, the brightness is clamped to the als high limit. if the minimum als setting is below 10%, the brightness is clamped to 10%. figure 7 shows the brightness change as a function of the als voltage. the als input voltage is sampled every dpwm period and is loaded in als status register 0x04. the analog voltage on the als pin is converted into an 8-bit digital code. the total number of brightness levels is 256. one step change results in a 0.391% change in the dpwm duty cycle. pwm mode in pwm mode, the MAX8759 sets the brightness based on the duty cycle of the pwmi signal. the absolute min- imum brightness is 10%. if the pwmi duty cycle is less than 10%, the brightness stays at 10%. the frequency range of the pwmi signal is between 5khz and 50khz when the pwmo capacitor is 1?. smbus mode in smbus mode, the MAX8759 sets the brightness based on the brightness control register (0x00). the brightness control register contains 8 bits and supports 256 brightness levels. a setting of 0xff for register 0x00 sets the inverter to the maximum brightness. a setting of 0x00 for register 0x00 sets the inverter to the minimum brightness (10%). als with dpst mode in als with dpst mode, the MAX8759 sets the bright- ness based on the analog voltage on the als pin and duty cycle at the pwmi pin. the MAX8759 lowers the als brightness setting by an additional amount that is proportional to the duty cycle of the pwmi signal. for example, if the als brightness setting is 80% and the duty cycle of pwmi signal is 60%, the resulting bright- ness setting is 80% x 60% = 48%. smbus with dpst mode in smbus with dpst mode, the MAX8759 sets the brightness based on the brightness control register (0x00). the MAX8759 lowers the smbus brightness set- ting by an additional amount that is proportional to the duty cycle of the pwmi signal. for example, if the brightness control register is set to 0x80 (correspond- ing to 50% brightness setting) and the duty cycle of the pwmi signal is 60%, the resulting brightness setting is 50% x 60% = 30%. fhzkr dpwm freq = 210 169 ? / low-cost, smbus, ccfl backlight controller 18 ______________________________________________________________________________________
fault protections lamp-out protection for safety, the MAX8759 monitors the lamp-current feedback inputs (ifb1 and ifb2) to detect faulty or open ccfl tubes. as described in the lamp-current regulation section, the voltage on ifb1 and ifb2 is internally full-wave rectified. if the rectified ifb1 or ifb2 voltage is below 600mv, the MAX8759 charges the tflt capacitor with 1?. the MAX8759 sets the fault latch and the device is shut down when the voltage on tflt exceeds 4v. unlike the normal shutdown mode, the linear regulator output (v cc ) remains at 5.35v. clearing bit 0 of the device control register (0x01) or cycling the input power clears the fault latch. during the fault-delay period, the current control loop tries to maintain the lamp-current regulation by increas- ing the high-side mosfet on-time. because the lamp impedance is very high when it is open, the transformer secondary voltage rises as a result of the high q-factor of the resonant tank. once the secondary voltage exceeds the overvoltage threshold, the MAX8759 turns on a 1000? current source that discharges the comp capacitor. the on-time of the high-side mosfet is reduced, lowering the secondary voltage as the comp voltage decreases. therefore, the peak voltage of the transformer secondary winding never exceeds the limit during the lamp-out delay period. primary overcurrent protection the MAX8759 senses primary current in each switch- ing cycle. when the regulator turns on the low-side mosfet, a comparator monitors the voltage drop from lx_ to pgnd_. if the voltage exceeds the current-limit threshold (430mv, typ), the regulator immediately turns off the high-side switch to prevent the transformer pri- mary current from increasing further. secondary voltage limiting (vfb) the MAX8759 reduces the voltage stress on the trans- former? secondary winding by limiting the secondary voltage during startup and open-lamp faults. the ac voltage across the transformer secondary winding is sensed through a capacitive voltage-divider formed by c4 and c5 in figure 1. the voltage across c5 is fed to the vfb input. an overvoltage comparator compares the vfb peak voltage with a 2.3v (typ) internal thresh- old. once the vfb peak voltage exceeds the overvolt- age threshold, the MAX8759 turns on an internal 1000? current source that discharges the comp capacitor. the high-side mosfet? on-time shortens as the comp voltage decreases, limiting the transformer secondary? peak voltage at the threshold determined by the capacitive voltage-divider. secondary undervoltage protection (vfb) the MAX8759 senses the vfb voltage for undervoltage condition. during the dpwm on period, if the vfb volt- age is below the undervoltage threshold (230mv, typ) continuously for an internal delay period (250? typ, for r freq = 169k ? ), the MAX8759 shuts down. secondary current limit (isec) the secondary current limit provides fail-safe current limiting in case of a short circuit or leakage from the lamp high-voltage terminal to ground that prevents the current control loop from functioning properly. isec monitors the voltage across a sense network placed between the transformer? low-voltage secondary termi- nal and ground. the isec voltage is continuously com- pared to the isec regulation threshold (1.21v, typ). any time the isec voltage exceeds the threshold, the MAX8759 turns on a 1000? current source that dis- charges the comp capacitor, reducing the on-time of the high-side switches. at the same time, the MAX8759 charges the tflt capacitor with a 135? current. the MAX8759 sets the fault latch and shuts down when the voltage on tflt exceeds 4v. clearing bit 0 of the device control register (0x01) or cycling the input power clears the fault latch. linear regulator output (v cc ) the internal linear regulator steps down the dc input voltage at batt pin to 5.35v (typ). the linear regulator supplies power to the internal control circuitry of the MAX8759 and is also used to power the mosfet dri- vers by connecting v cc to v dd . the v cc voltage drops to 4.5v in shutdown. por and uvlo the MAX8759 includes power-on reset (por) and undervoltage lockout (uvlo) features. por resets the fault latch and sets all the smbus registers to their por MAX8759 low-cost, smbus, ccfl backlight controller ______________________________________________________________________________________ 19 0 0.2 0.6 0.4 0.8 1.0 0 0.8 0.4 1.2 1.6 2.0 v als (v) normalized brightness figure 7. normalized brightness vs. als voltage
MAX8759 values. por occurs when v cc rises above 1.75v (typ). the uvlo occurs when v cc is below 4.2v (typ). the MAX8759 disables both high-side and low-side switch drivers below the uvlo threshold. low-power shutdown the MAX8759 is placed into shutdown by clearing bit 0 of the device control register (0x01).when the MAX8759 is shut down, all functions of the ic are turned off except the 5.35v linear regulator. in shut- down, the linear regulator output voltage drops to 4.5v and the supply current is 6a (typ). while in shutdown, the fault latch is reset. the device can be reenabled by setting bit 0 of the device control register to 1. ambient-light-sensor supply pin (vals) the MAX8759 provides the supply voltage of the als through the vals pin. vals is internally connected to the 5.35v linear regulator output through a p-channel mosfet. the p-channel mosfet is turned on when the MAX8759 is enabled and turned off when the part is dis- abled. bypass vals to ground with a minimum 0.l? ceramic capacitor. place the capacitor as close to the als supply input as possible. smbus interface (sda, scl) the MAX8759 supports an smbus-compatible 2-wire digital interface. sda is the bidirectional data line and scl is the clock line of the 2-wire interface correspond- ing respectively to smbdata and smbclk lines of the smbus. sda and scl have schmidt-triggered inputs that can accommodate slow edges; however, the rising and falling edges should still be faster than 1? and 300ns, respectively. the MAX8759 uses the write-byte and read-byte protocols (figure 8). the smbus proto- cols are documented in system management bus specification v1.08 and are available at http://www.sbs-forum.org/. the MAX8759 is a slave-only device and responds to the 7-bit address 0b0101100. the read and write com- mands can be distinguished by adding one more bit (r/ w bit) to the end of the 7-bit slave address, with one indicating read and zero indicating write. the MAX8759 has seven registers: a brightness control register (0x00), a device control register (0x01), a fault/status register (0x02), an identification register (0x03), an als status register (0x04), an als low-limit register (0x05), low-cost, smbus, ccfl backlight controller 20 ______________________________________________________________________________________ 1b ack 1b 7 bits address ack 1b wr 8 bits data 1b ack p 8 bits s command write-byte format receive-byte format slave address data byte: data goes into the register set by the command byte 1b ack 1b 7 bits address ack 1b wr s 1b ack 8 bits data 7 bits address 1b rd 1b 8 bits /// p s command slave address slave address command byte: sends com- mand with no data; usually used for one-shot command command byte: selects which register you are reading from slave address: repeated due to change in data- flow direction data byte: reads from the register set by the command byte 1b ack 7 bits address 1b rd 8 bits data 1b /// p s data byte: reads data from the register commanded by the last read-byte or write-byte transmission; also used for smbus alert response return address s = start condition shaded = slave transmission wr = write = 0 p = stop condition ack = acknowledged = 0 rd = read = 1 /// = not acknowledged = 1 1b ack 7 bits address 1b wr 8 bits command 1b ack p s send-byte format read-byte format figure 8. smbus protocols command byte: selects which register you are writing to
and an als high-limit register (0x06). the MAX8759 only acknowledges these seven registers. communication starts with the master signaling the beginning of a transmission with a start condition, which is a high-to-low transition on sda while scl is high. when the master has finished communicating with the slave, the master issues a stop condition, which is a low-to-high transition on sda while scl is high. the bus is then free for another transmission. figures 9 and 10 show the timing diagrams for signals on the 2-wire interface. the address byte, command byte, and data byte are transmitted between the start and stop conditions. the sda state is allowed to change only while scl is low, except for the start and stop conditions. data is transmitted in 8-bit words and is sampled on the rising edge of scl. nine clock cycles are required to transfer each byte in or out of the MAX8759 since either the master or the slave acknowl- edges the receipt of the correct byte during the ninth clock. if the MAX8759 receives its correct slave address followed by r/ w = 0, it expects to receive 1 or 2 bytes of information (depending on the protocol). if the device detects a start or stop condition prior to clocking in the bytes of data, it considers this an error condition and disregards all the data. if the transmis- sion is completed correctly, the registers are updated immediately after a stop (or restart) condition. if the MAX8759 receives its correct slave address fol- lowed by r/ w = 1, it expects to clock out the register data selected by the previous command byte. smbus register definitions all MAX8759 registers are byte wide and accessible through the read/write byte protocols mentioned in the previous section. their bit assignments are provided in the following sections with reserved bits containing a default value of zero. table 3 summarizes the register assignments, as well as each register? por state. during shutdown, the ser- ial interface remains fully functional. MAX8759 low-cost, smbus, ccfl backlight controller ______________________________________________________________________________________ 21 smbclk ab cd e fg h i j k smbdata t su:sta t hd:sta t low t high t su:dat t hd:dat t hd:dat t su:sto t buf a = start condition. b = msb of address clocked into slave. c = lsb of address clocked into slave. d = r/w bit clocked into slave. e = slave pulls smbdata line low . l m f = acknowledge bit clocked into master. g = msb of data clocked into slave. h = lsb of data clocked into slave. i = slave pulls smbdata line low. j = acknowledge clocked into master. k = acknowledge clock pulse. l = stop condition, data executed by slave. m = new start condition . figure 9. smbus write timing
MAX8759 low-cost, smbus, ccfl backlight controller 22 ______________________________________________________________________________________ table 3. commands description data-register bit assignment smbus protocol command byte por state bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) read and write 0x00 0xff br7 brt6 brt5 br4 brt3 brt2 brt1 brt0 read and write 0x01 0x00 reserved reserved alsdel1 alsdel0 als_ctl pwm_md pwm_sel lamp_ctl read only 0x02 n/a reserved reserved reserved reserved lamp_stat ov_curr reserved fault read only 0x03 0x01 mfg4 mfg3 mfg2 mfg1 mfg0 rev2 rev1 rev0 read only 0x04 0x00 als7 als6 als5 als4 als3 als2 als1 als0 read and write 0x05 0x00 alsll7 alsll6 alsll5 alsll4 alsll3 alsll2 alsll1 alsll0 read and write 0x06 0xff alshl7 alshl6 alshl5 alshl4 alshl3 alshl2 alshl1 alshl0 smbclk a = start condition. b = msb of address clocked into slave. c = lsb of address clocked into slave. d = r/w bit clocked into slave. ab cd e fg h i j smbdata t su:sta t hd:sta t low t high t su:dat t hd:dat t su:dat t su:sto t buf k e = slave pulls smbdata line low. f = acknowledge bit clocked into master. g = msb of data clocked into master. h = lsb of data clocked into master. i = acknowledge clock pulse. j = stop condition. k = new start condition. figure 10. smbus read timing
MAX8759 low-cost, smbus, ccfl backlight controller ______________________________________________________________________________________ 23 bit 7 bit 6 bit 5 (r/ w ) bit 4 (r/ w ) bit 3 (r/ w ) bit 2 (r/ w ) bit 1 (r/ w ) bit 0 (r/ w ) reserved reserved alsdel1 alsdel0 als_ctl pwm_md pwm_sel lamp_ctl alsdel1: als delay select bit. alsdel0: als delay select bit. als_ctl: ambient-light-sensor select bit (1 = use als, 0 = not use als). pwm_md: pwm mode select bit (1 = absolute brightness, 0 = percentage change). pwm_sel: brightness control select bit (1 = control by pwm, 0 = control by smbus). lamp_ctl: inverter on/off bit (1 = on, 0 = off). a value of 1 written to lamp_ctl turns on the lamp as quickly as possible. a value of zero written to lamp_ctl immediately turns off the lamp. the pwm_sel bit determines whether the smbus or pwm input should control brightness when the inverter is not in als mode. this bit has no effect when als_ctl is set to 1. the pwm_md bit selects the manner in which the pwm input is to be interpreted. when this bit is zero, the pwm input reflects a percentage change in the current bright- ness (i.e., dpst mode) and follows the following equation: dpst brightness = brt current d pwm where brt current is the current brightness setting from either als or smbus without influence from the pwm input and d pwm is the duty cycle of the pwm signal. when pwm_md bit is 1, the pwm input has no effect on the brightness setting unless the inverter is in pwm mode. when als_ctl is 1, the inverter controls brightness based primarily on the light reading from the als. however, the als brightness setting can be modified if the pwm_md bit is set to zero. when the als_ctl bit is zero, the inverter controls the brightness according to the pwm input (pwm mode), the smbus setting (smbus mode), or a combination of the two (smbus mode with dpst). bit 7 (r/ w ) bit 6 (r/ w ) bit 5 (r/ w ) bit 4 (r/ w ) bit 3 (r/ w ) bit 2 (r/ w ) bit 1 (r/ w ) bit 0 (r/ w ) brt7 brt6 brt5 brt4 brt3 brt2 brt1 brt0 brt[7..0]: 256 brightness levels. brightness control register [0x00] (por = 0xff) the brightness control register of the MAX8759 con- tains 8 bits and supports 256 brightness levels. a write- byte cycle to register 0x00 sets the brightness level if the inverter is in smbus mode. a write-byte cycle to register 0x00 has no effect if the inverter is not in smbus mode. a read-byte cycle to register 0x00 returns the current brightness level regardless of the operation mode. a setting of 0xff for register 0x00 sets the inverter to the maximum brightness. a setting of 0x00 for register 0x00 sets the inverter to the minimum brightness. device control register [0x01] (por = 0x00) this register has a single bit that controls the inverter on/off state, 3 bits that control the operating mode of the inverter, and 2 bits for setting als delay time. the remaining bits are reserved for future use.
MAX8759 the relationships among these 3 control bits can be thought of as specifying an operating mode for the invert- er. the defined modes are shown in table 4. note that depending on the settings of some bits, other bits have no effect and are don?-care bits?hey are shown with a value of x in table 4. for example, when the als_ctl bit is 1, the value of pwm_sel has no effect on the operation of the inverter, so its value is shown as x. alsdel0 and alsdel1 set the delay time required to change the brightness in als mode. this delay time is necessary for smooth transitions during brightness change. table 5 shows the available delays. note that the behavior of register 0x00 (brightness con- trol register) is affected by certain combinations of the control bits as shown in table 4. when smbus mode is selected, register 0x00 reflects the last value written to it. however, when any non-smbus mode is selected, register 0x00 reflects the current bright- ness value based on the current mode of operation. fault/status register [0x02] (por = 0x00) this register has 3 status bits that allow monitoring the inverter? operating state. bit 0 is a logical or of open- lamp fault and overcurrent fault. bit 2 indicates sec- ondary/ul overcurrent fault. bit 3 always indicates the current lamp on/off status. the value of this bit is one whenever both lamp 1 and lamp 2 are on. the value of this bit is zero whenever lamp 1 or lamp 2 is off. the remaining bits are reserved for future use. all reserved bits return a zero when read. all the bits in this register are read only. a write-byte cycle to register 0x02 has no effect. write zero to bit 0 of register 0x01 to clear the fault bit. low-cost, smbus, ccfl backlight controller 24 ______________________________________________________________________________________ als_ctl pwm_md pwm_sel mode 1 1 x als mode 1 0 x als mode with dpst 0 x 1 pwm mode 0 1 0 smbus mode 000 smbus mode with dpst alsdel1 alsdel0 delay time (ms) n periods 1 1 25 5 1 0 15 3 0 1 10 2 0 0 20 (default) 4 bit 7 (r) bit 6 (r) bit 5 (r) bit 4 (r) bit 3 (r) bit 2 (r) bit 1 (r) bit 0 (r) reserved reserved reserved reserved lamp_stat ov_curr reserved fault lamp_stat: lamp status bit (1 = lamp 1 and lamp 2 are on, 0 = lamp 1 or lamp 2 is off). ov_curr: secondary/ul overcurrent fault (1 = secondary/ul overcurrent fault, 0 = no secondary/ul overcurrent). fault: fault bit (1 = open-lamp or primary overcurrent fault, 0 = no fault). table 4. operating modes selected by device control register bits 3, 2, and 1 table 5. delay time selected by device control register bits 5, 4
MAX8759 low-cost, smbus, ccfl backlight controller ______________________________________________________________________________________ 25 bit 7 (r) bit 6 (r) bit 5 (r) bit 4 (r) bit 3 (r) bit 2 (r) bit 1 (r) bit 0 (r) mfg4 mfg3 mfg2 mfg1 mfg0 rev2 rev1 rev0 mfg[4..0]: manufacturer id (the vendor id for maxim is 0). rev[2..0]: silicon rev (revs 0? allowed for silicon revisions). bit 7 (r) bit 6 (r) bit 5 (r) bit 4 (r) bit 3 (r) bit 2 (r) bit 1 (r) bit 0 (r) als7 als6 als5 als4 als3 als2 als1 als0 als[7..0]: 256 steps of ambient-light sensor reading. identification register [0x03] (por = 0x01) the identification register contains two bit fields to denote the manufacturer and the silicon revision. the bit field widths allow up to 32 vendors with up to eight sili- con revisions each. this register is read only. a write- byte cycle to register 0x03 has no effect. als status register [0x04] (por = 0x00) the als should return a value reflecting the brightness setting based on the als input. the register has 8 bits that define a full range of 256 brightness levels. the register is read only and a write-byte cycle has no effect. a read-byte cycle to register 0x04 returns the current reading of als, regardless of the operating mode set in register 0x01. als low-limit register [0x05] (por = 0x00) the value in this read-write register reflects the lowest possible brightness value the inverter can set based on inputs from the als. users can change this value so that they can control the effect of als. a write-byte cycle to register 0x05 sets the lowest possible brightness value that can be set based on als inputs. if the brightness setting due to als is lower than the value written to this register, the inverter immediately increases the bright- ness setting to the newly written value. a read-byte cycle to register 0x05 returns the current minimum brightness value that can be set based on als inputs. bit 7 (r/ w ) bit 6 (r/ w ) bit 5 (r/ w ) bit 4 (r/ w ) bit 3 (r/ w ) bit 2 (r/ w ) bit 1 (r/ w ) bit 0 (r/ w ) alsll7 alsll6 alsll5 alsll4 alsll3 alsll2 alsll1 alsll0 alsll[7..0]: the lowest brightness setting that can be set based on als inputs.
MAX8759 applications information mosfets the MAX8759 requires four external n-channel power mosfets: nl1, nl2, nh1, and nh2 to form a full- bridge inverter circuit. the controller senses the on-state drain-to-source voltage of the two low-side mosfets nl1 and nl2 to detect the transformer primary current, so the r ds(on) of nl1 and nl2 should be matched. for instance, if dual mosfets are used to form the full bridge, nl1 and nl2 should be in one package. since the MAX8759 uses the low-side mosfet r ds(on) for primary overcurrent protection, the lower the mosfet r ds(on) , the higher the current limit. therefore, the user should select a dual logic-level n-channel mosfet with low r ds(on) to minimize conduction loss, and keep the primary current limit at a reasonable level. the regulator uses zvs to softly turn on each of four switches in the full bridge. zvs occurs when the exter- nal power mosfets are turned on when their respec- tive drain-to-source voltages are near 0v (see the resonant operation section). zvs effectively eliminates the instantaneous turn-on loss of mosfets caused by c oss (drain-to-source capacitance) and parasitic capacitance discharge, and improves efficiency and reduces switching-related emi. setting the lamp current the MAX8759 senses the lamp current flowing through sense resistors connected between the low-voltage ter- minals of the lamps and ground. the voltages across the sense resistors are fed to ifb1 and ifb2 and are internally full-wave rectified. the MAX8759 controls the desired lamp current by regulating the average of the rectified ifb_ voltages. to set the rms lamp current in a single-lamp application, determine the value of the sense resistor as follows: where i lamp(rms) is the desired rms lamp current and 785mv is the typical value of the ifb1 regulation point specified in the electrical characteristics table. to set the rms lamp current to 6ma, the value of the sense resistor should be 148 ? . the closest standard 1% resistors are 147 ? and 150 ? . the precise shape of the lamp-current waveform, which is dependent on lamp parasitics, influences the actual rms lamp current. use a true rms current meter to make final adjustments. setting the secondary voltage limit the MAX8759 limits the transformer secondary voltage during startup and lamp-out faults. the secondary volt- age is sensed through the capacitive voltage-divider formed by c4 and c5 (figure 1). the vfb voltage is proportional to the ccfl voltage. the selection of the parallel resonant capacitor c1 is described in the transformer design and resonant component selection section. c4 is usually between 10pf and 22pf. after the value of c4 is determined, select c5 r mv i lamp rms 1 785 22 = () low-cost, smbus, ccfl backlight controller 26 ______________________________________________________________________________________ bit 7 (r/ w ) bit 6 (r/ w ) bit 5 (r/ w ) bit 4 (r/ w ) bit 3 (r/ w ) bit 2 (r/ w ) bit 1 (r/ w ) bit 0 (r/ w ) alshl7 alshl6 alshl5 alshl4 alshl3 alshl2 alshl1 alshl0 alshl[7..0]: the highest brightness setting that can be set based on als inputs. als high-limit register [0x06] (por = 0xff) the value in this read-write register reflects the highest possible brightness value the inverter can set based on inputs from the als. users can change this value so that they can control the effect of als. a write-byte cycle to register 0x06 sets the highest possible bright- ness value that can be set based on als inputs. if the brightness setting due to als is higher than the value written to this register, the inverter immediately decreas- es the brightness setting to the newly written value. a read-byte cycle to register 0x06 returns the current maximum brightness value that can be set based on als inputs. the default value of register 0x06 is 0xff, which corresponds to the maximum brightness.
using the following equation to set the desired maxi- mum rms secondary voltage v lamp(rms) _ max : where the 2.3v is the typical value of the vfb peak volt- age when the lamp is open. to set the maximum rms secondary voltage to 1800v when c4 is 10pf, use 10nf for c5. setting the secondary current limit the MAX8759 limits the secondary current even if the ifb_ sense resistors are shorted or transformer sec- ondary current finds its way to ground without passing through the sense resistors. isec monitors the peak volt- age across the sense network (r2 and c6 in figure 1) connected between the low-voltage terminal of the trans- former secondary winding and ground. using an rc- sense network instead of a single-sense resistor makes the secondary current-limit frequency dependent. the ul safety standard requires the ac peak current in a limited- current circuit should not exceed 0.7ma for frequencies below 1khz. for frequencies above 1khz, the limit of 0.7ma is multiplied by the value of the frequency in kilo- hertz but should not exceed 70ma peak when the fre- quency is equal to or above 100khz. to meet the ul current-limit specifications, determine the value of r2 using the current limit at 1khz and determine the value of c6 using the current limit at 100khz: where 1.23v is the typical value of the isec peak volt- age when the transformer secondary is shorted. the circuit of figure 1 uses 3.9k ? for r2 and 68nf for c6. transformer design and resonant component selection the transformer is the most important component of the resonant tank circuit. the first step in designing the transformer is to determine the transformer turns ratio. the ratio must be high enough to support the ccfl operating voltage at the minimum supply voltage. the transformer turns ratio n can be calculated as follows: where v lamp(rms) is the maximum rms lamp voltage in normal operation, and v in(min) is the minimum dc input voltage. if the maximum rms lamp voltage in normal oper- ation is 700v and the minimum dc input voltage is 7.5v, the turns ratio should be greater than 104. the turns ratio of the transformer used in the circuit of figure 1 is 110. the next step in the design procedure is to determine the desired operating frequency range. the MAX8759 is syn- chronized to the natural resonant frequency of the reso- nant tank. the resonant frequency changes with operating conditions, such as the input voltage, lamp impedance, etc. therefore, the switching frequency varies over a certain range. to ensure reliable operation, the resonant frequency range must be within the operat- ing frequency range specified by the ccfl transformer manufacturer. as discussed in the resonant operation section, the resonant frequency range is determined by transformer secondary leakage inductance l, the primary series dc blocking capacitors (c s ), and the secondary parallel resonant capacitor c p . since it is difficult to con- trol the transformer leakage inductance, the resonant tank design should be based on the existing secondary leak- age inductance of the selected ccfl transformer. the leakage inductance values can have large tolerance and significant variations among different batches. it is best to work directly with transformer vendors on leakage induc- tance requirements. the MAX8759 works best when the secondary leakage inductance is between 250mh and 350mh. series capacitor c s sets the minimum operating frequency, which is approximately two times the series resonant peak frequency. choose: where f min is the minimum operating frequency range. in the circuit of figure 1, the transformer? turns ratio is 110 and its secondary leakage inductance is approxi- mately 300mh. to set the minimum operating frequen- cy to 30khz, the total series capacitance needs to be less than 4.5?. therefore, two 2.2? capacitors (c2 and c3) are used in figure 1. parallel capacitor c p sets the maximum operating fre- quency, which is also the parallel resonant peak fre- quency. choose: in the circuit of figure 1, to set the maximum operating frequency to 100khz, c p needs to be larger than 8.6pf. a 10pf high-voltage capacitor (c4) is used in figure 1. c c flcn p s max s ? 4 22 2 c n fl s min 2 22 n v v lamp rms in min () () . 09 c ma khz v nf 6 70 2 100 1 23 90 < = . r v ma k 2 123 07 175 >= . . . ? c v v c lamp rms max 5 2 23 4 = ()_ . MAX8759 low-cost, smbus, ccfl backlight controller ______________________________________________________________________________________ 27
MAX8759 the transformer core saturation should also be consid- ered when selecting the operating frequency. the pri- mary winding should have enough turns to prevent transformer saturation under all operating conditions. use the following expression to calculate the minimum number of turns n1 of the primary winding: where d max is the maximum duty cycle (approximately 0.8) of the high-side switches, v in(max) is the maximum dc input voltage, b s is the saturation flux density of the core, and s is the minimal cross-section area of the core. comp capacitor selection the comp capacitor sets the speed of the current loop that is used during startup, maintaining lamp-current regulation, and during transients caused by changing the input voltage. to maintain stable operation, the comp capacitor (c comp ) needs to be at least 3.3nf. the comp capacitor also limits the dynamics of the lamp-current envelope in dpwm operation. at the end of the dpwm on cycle, the MAX8759 turns on a 110? internal current source to linearly discharge the comp capacitor. use the following equation to set the fall time: where t fall is the fall time of the lamp-current envelope and v comp is the comp voltage when the lamp current is in regulation. at the beginning of the dpwm on cycle, the comp capacitor is charged by a transconductance error amplifier. the rise time is about three times longer than the fall time. setting the fault-delay time the tflt capacitor determines the delay time for both the open-lamp fault and secondary short-circuit fault. the MAX8759 charges the tflt capacitor with a 1? current source during an open-lamp fault and charges the tflt capacitor with a 135? current source during a secondary short-circuit fault. therefore, the sec- ondary short-circuit fault delay time is approximately 135 times shorter than that of open-lamp fault. the MAX8759 sets the fault latch when the tflt voltage reaches 4v. use the following equations to calculate the open-lamp fault delay (t open _ lamp ) and sec- ondary short-circuit fault delay (t sec _ short ): bootstrap capacitors the high-side gate drivers are powered using two boot- strap circuits. the MAX8759 integrates the bootstrap diodes so only two 0.1? bootstrap capacitors are needed. connect the capacitors (c10 and c11 in figure 1) between lx1 and bst1, and between lx2 and bst2 to complete the bootstrap circuits. dual-lamp operating circuit the MAX8759 includes two lamp current feedback input pins that support dual-lamp applications with a minimum number of external components. figure 11 shows the typical dual-lamp operating circuit. layout guidelines careful pc board layout is important to achieve stable operation. the high-voltage section and the switching section of the circuit require particular attention. the high-voltage sections of the layout need to be well sep- arated from the control circuit. most layouts for single- lamp notebook displays are constrained to long and narrow form factors, so this separation occurs naturally. follow these guidelines for good pc board layout: 1) keep the high-current paths short and wide, espe- cially at the ground terminals. this is essential for stable, jitter-free operation and high efficiency. 2) use a star ground configuration for power and ana- log grounds. the power and analog grounds should be completely isolated?eeting only at the center of the star. the center should be placed at the analog ground pin (gnd). using separate cop- per islands for these grounds can simplify this task. quiet analog ground is used for v cc , comp, freq, and tflt. 3) route high-speed switching nodes away from sensi- tive analog areas (v cc , comp, freq, and tflt). make all pin-strap control input connections to ana- log ground or v cc rather than power ground or v dd . 4) mount the decoupling capacitor from v cc to gnd as close as possible to the ic with dedicated traces that are not shared with other signal paths. 5) the current-sense paths for lx1 and lx2 to gnd must be made using kelvin-sense connections to guarantee the current-limit accuracy. with 8-pin so mosfets, this is best done by routing power to the mosfets from outside, using the top copper layer, while connecting gnd and lx inside (underneath) the 8-pin so package. t cv a sec short tflt _ = 4 135 t cv a open lamp tflt _ = 4 1 c at v comp fall comp = 110 n dv bsf max in max smin 1 > () low-cost, smbus, ccfl backlight controller 28 ______________________________________________________________________________________
MAX8759 low-cost, smbus, ccfl backlight controller ______________________________________________________________________________________ 29 n2a 19 24 21 1 c7 0.1 f c8 1 f c1 22 f 25v c10 0.1 f c11 0.1 f c13 6.8nf c4 10pf 3kv r1 150 ? 1% r14 100k ? r15 100k ? r2 150k ? 1% r8 390k ? 1% r7 390k ? 1% r9 180k ? r10 20k ? r12 180k ? r13 20k ? c17 1nf c6 1nf c5 10pf 3kv c3 2.2 f c2 2.2 f t1 1:110 t2 1:110 hv lv 2 1 c14 0.22 f fds6990a fds6990a c9 0.47 f c12 1 f c15 0.1 f r3 169k ? 1% v cc 27 11 28 2 3 7 8 9 5 6 batt gnd del v cc v cc sda scl pwmi pwmo freq vals als 18 17 16 26 20 23 22 25 12 13 15 14 10 4 pgnd1 bst2 v dd bst1 gh1 lx1 lx2 gl1 pgnd2 gl2 gh2 ifb1 ifb2 isec vfb comp tflt n2b d3 d4 n1a n1b pwm input input voltage smb_data smb_clock f1 2a als supply als output 7.5v to 21v MAX8759 hv lv 2 1 figure 11. typical max8758 dual-lamp operating circuit
MAX8759 6) ensure the feedback connections are short and direct. to the extent possible, ifb1, ifb2, vfb, and isec connections should be far away from the high- voltage traces and the transformer. 7) to the extent possible, high-voltage trace clearance on the transformer? secondary should be widely separated. the high-voltage traces should also be separated from adjacent ground planes to prevent lossy capacitive coupling. 8) the traces to the capacitive voltage-divider on the transformer? secondary need to be widely separated to prevent arcing. moving these traces to opposite sides of the board can be beneficial in some cases. low-cost, smbus, ccfl backlight controller 30 ______________________________________________________________________________________ chip information transistor count: 16,138 process: bicmos 28 27 26 25 24 23 22 8 9 10 11 12 13 14 15 16 17 18 19 20 21 7 6 5 4 3 2 1 MAX8759 *exposed paddle tqfn 5mm x 5mm top view sda batt scl tflt vals als pwmi v cc gnd lx2 gh2 bst2 pgnd2 gl2 v dd gl1 pgnd1 bst1 gh1 lx1 isec vfb ifb2 ifb1 del comp freq pwmo pin configuration
MAX8759 low-cost, smbus, ccfl backlight controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 31 2006 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 d/2 d2/2 l c l c e e l c c l k l l detail b l l1 e aaaaa marking i 1 2 21-0140 package outline, 16, 20, 28, 32, 40l thin qfn, 5x5x0.8mm -drawing not to scale- l e/2 common dimensions max. exposed pad variations d2 nom. min. min. e2 nom. max. ne nd pkg. codes 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220, except exposed pad dimension for t2855-3 and t2855-6. notes: symbol pkg. n l1 e e d b a3 a a1 k 10. warpage shall not exceed 0.10 mm. jedec 0.70 0.80 0.75 4.90 4.90 0.25 0.25 0 -- 4 whhb 4 16 0.35 0.30 5.10 5.10 5.00 0.80 bsc. 5.00 0.05 0.20 ref. 0.02 min. max. nom. 16l 5x5 l 0.30 0.50 0.40 -- - -- - whhc 20 5 5 5.00 5.00 0.30 0.55 0.65 bsc. 0.45 0.25 4.90 4.90 0.25 0.65 - - 5.10 5.10 0.35 20l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-1 28 7 7 5.00 5.00 0.25 0.55 0.50 bsc. 0.45 0.25 4.90 4.90 0.20 0.65 - - 5.10 5.10 0.30 28l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-2 32 8 8 5.00 5.00 0.40 0.50 bsc. 0.30 0.25 4.90 4.90 0.50 - - 5.10 5.10 32l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. 0.20 0.25 0.30 down bonds allowed yes 3.10 3.00 3.20 3.10 3.00 3.20 t2055-3 3.10 3.00 3.20 3.10 3.00 3.20 t2055-4 t2855-3 3.15 3.25 3.35 3.15 3.25 3.35 t2855-6 3.15 3.25 3.35 3.15 3.25 3.35 t2855-4 2.60 2.70 2.80 2.60 2.70 2.80 t2855-5 2.60 2.70 2.80 2.60 2.70 2.80 t2855-7 2.60 2.70 2.80 2.60 2.70 2.80 3.20 3.00 3.10 t3255-3 3 3.20 3.00 3.10 3.20 3.00 3.10 t3255-4 3 3.20 3.00 3.10 no no no no yes yes yes yes 3.20 3.00 t1655-3 3.10 3.00 3.10 3.20 no no 3.20 3.10 3.00 3.10 t1655n-1 3.00 3.20 3.35 3.15 t2055-5 3.25 3.15 3.25 3.35 yes 3.35 3.15 t2855n-1 3.25 3.15 3.25 3.35 no 3.35 3.15 t2855-8 3.25 3.15 3.25 3.35 yes 3.20 3.10 t3255n-1 3.00 no 3.20 3.10 3.00 l 0.40 0.40 ** ** ** ** ** ** ** ** ** ** ** ** ** ** see common dimensions table 0.15 11. marking is for package orientation reference only. i 2 2 21-0140 package outline, 16, 20, 28, 32, 40l thin qfn, 5x5x0.8mm -drawing not to scale- 12. number of leads shown are for reference only. 3.30 t4055-1 3.20 3.40 3.20 3.30 3.40 ** yes 0.05 0 0.02 0.60 0.40 0.50 10 ----- 0.30 40 10 0.40 0.50 5.10 4.90 5.00 0.25 0.35 0.45 0.40 bsc. 0.15 4.90 0.25 0.20 5.00 5.10 0.20 ref. 0.70 min. 0.75 0.80 nom. 40l 5x5 max. 13. lead centerlines to be at true position as defined by basic dimension "e", 0.05. t1655-2 ** yes 3.20 3.10 3.00 3.10 3.00 3.20 t3255-5 yes 3.00 3.10 3.00 3.20 3.20 3.10 ** exceptions

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